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VLSI Based IEEE Projects Projects

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ID Project Title Action
VL001 Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators (IEEE - 2016)
VL002 Hyper graph Based Minimum Arborescence Algorithm for the Optimization and Reoptimization of Multiple Constant Multiplications. (IEEE - 2016)
VL003 A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic (IEEE - 2016)
VL004 Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication (IEEE - 2016)
VL005 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits (IEEE - 2016)
VL006 Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design (IEEE - 2016)
VL007 CORDIC II: A New Improved CORDIC Algorithm (IEEE - 2016)
VL008 Low-Power Parallel Chien Search Architecture Using a Two-Step Approach
VL009 Efficient Circuit for Parallel Bit Reversal (IEEE - 2016)
VL010 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels (IEEE - 2016)
VL011 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication (IEEE - 2016)
VL012 A High-Performance FIR Filter Architecture for Fixed and Recon?gurable Applications (IEEE - 2016)
VL013 Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems (IEEE - 2016)
VL014 Improving Nested Loop Pipelining on Coarse-Grained Recon?gurable Architectures (IEEE - 2016)
VL015 One-Cycle Correction of Timing Errors in Pipelines with Standard Clocked Elements (IEEE - 2016)
VL016 Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs with Performance Analysis (IEEE - 2016)
VL017 A New Optimal Algorithm for Energy Saving in Embedded System with Multiple Sleep Modes (IEEE - 2016)
VL018 A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM (IEEE - 2016)
VL019 Input-Based Dynamic Recon?guration of Approximate Arithmetic Units for Video Encoding (IEEE - 2016)
VL020 Ultralow-Energy Variation-Aware Design: Adder Architecture Study (IEEE - 2016)
VL021 SRAM-Based Unique Chip Identi?er Techniques (IEEE - 2016)
VL022 Implementing Minimum-Energy-Point Systems with Adaptive Logic (IEEE - 2016)
VL023 On Efficient Retiming of Fixed-Point Circuits (IEEE - 2016)
VL024 Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers (IEEE - 2016)
VL025 Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip (IEEE - 2016)
VL026 Concept, Design, and Implementation of Recon?gurable CORDIC (IEEE - 2016)
VL027 A New CDMA Encoding/Decoding Method for on-Chip Communication Network (IEEE - 2016)
VL028 Low-Cost On-Chip Clock Jitter Measurement Scheme (IEEE-2015)
VL029 Z-TCAM: An SRAM-based Architecture for TCAM (IEEE-2015)
VL030 Quaternary Logic Lookup Table in Standard CMOS (IEEE-2015)
VL031 A Low-Jitter Cell-Based Digitally Controlled Oscillator with Differential Multiphase Outputs (IEEE-2015)
VL032 Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path (IEEE-2015)
VL033 Accumulator based 3-Weight Pattern Generation (IEEE-2015)
VL034 A Low Power BIST for High Fault Coverage (IEEE-2015)
VL035 A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator (IEEE-2015)
VL036 All Digital Energy Sensing for Minimum Energy Tracking (IEEE-2015)
VL037 Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs achieving ±1 LSB INL (IEEE-2015)
VL038 A CMOS PWM Transceiver Using Self-Referenced Edge Detection (IEEE-2015)
VL039 Diagnosis and Layout Aware (DLA) Scan Chain Stitching (IEEE-2015)
VL040 Supply-Noise Interactions among Sub modules Inside a Charge-Pump PLL (IEEE-2015)
VL041 A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks (IEEE-2015)
VL042 An Inter/Intra-Chip Optical Network for Many core Processors (IEEE-2015)
VL043 An I/O Efficient Model Checking Algorithm for Large-Scale Systems (IEEE-2015)
VL044 Constructions of Memory less Crosstalk Avoidance Codes via C-Transform (IEEE-2015)
VL045 Dynamic Thermal Estimation Methodology for High Performance 3-D MP SoCs (IEEE-2015)
VL046 Design Techniques to Improve Blocker Tolerance of Continuous-Time ADCs (IEEE-2015)
VL047 Design of Efficient Content Addressable Memories in High-Performance Fin FET Technology (IEEE-2015)
VL048 Characterization of the Proximity Effect from Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs (IEEE-2015)
VL049 Area–Delay–Power Efficient Carry-Select Adder (IEEE-2015)
VL050 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay (IEEE-2015)
VL051 LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation (IEEE-2015)
VL052 A VHDL Implementation of UART design with BIST capability (IEEE-2015)
VL053 A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC with Signal-Independent Delta-I Noise DFT Scheme (IEEE-2015)
VL054 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations (IEEE-2015)
VL055 Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging (IEEE-2015)
VL056 Wear out Resilience in NoCs through an Aging Aware Adaptive Routing Algorithm (IEEE-2015)
VL057 Implementation of Orthogonal Transmitter/Receiver (IEEE-2015)
VL058 FPGA Based Design of a Novel Enhanced Error Detection and Correction Technique (IEEE-2015)
VL059 Functional Constraint Extraction from Register Transfer Level for ATPG (IEEE-2015)
VL060 An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS (IEEE-2015)
VL061 Critical-path analysis and low-complexity implementation of the LMS Adaptive algorithm (IEEE-2015)
VL062 Level-Converting Retention Flip-Flop for Reducing Standby Power in Zigbee SoCs (IEEE-2015)
VL063 Z-TCAM: An SRAM-based Architecture for TCAM (IEEE-2015)
VL064 An Offset-Canceling Triple-Stage Sensing Circuit for Deep Sub micrometer STT-RAM (IEEE-2015)
VL065 Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set (IEEE-2015)
VL066 Recursive Approach to the Design of a Parallel Self-Timed Adder (IEEE-2015)
VL067 Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation (IEEE-2015)
VL068 VLSI Design of a Large-Number Multiplier for Fully Homomorphic Encryption (IEEE-2015)
VL069 Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory (IEEE-2015)
VL070 Fault Tolerant Parallel Filters Based on Error Correction Codes (IEEE-2015)
VL071 The Impact of Aging on a Physical Unclonable Function (IEEE-2015)
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